Freescale Semiconductor /MKL25Z4 /MCG /C6

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Interpret as C6

743000000000000VDIV00 (0)CME00 (0)PLLS0 (0)LOLIE0

LOLIE0=0, CME0=0, PLLS=0

Description

MCG Control 6 Register

Fields

VDIV0

VCO 0 Divider

CME0

Clock Monitor Enable

0 (0): External clock monitor is disabled for OSC0.

1 (1): External clock monitor is enabled for OSC0.

PLLS

PLL Select

0 (0): FLL is selected.

1 (1): PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).

LOLIE0

Loss of Lock Interrrupt Enable

0 (0): No interrupt request is generated on loss of lock.

1 (1): Generate an interrupt request on loss of lock.

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